1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to a semiconductor device having tiles for dual-trench integration and method therefor.
2. Related Art
During the manufacture of a semiconductor device, it may be necessary to planarize the surface of a semiconductor device as one or more of the manufacturing steps. Chemical Mechanical Polishing (CMP) is one such process used to planarize surfaces of semiconductor devices. However, it is difficult to guarantee uniformity of the planarization because of varying layouts on the semiconductor device. The non-uniformity in thickness, caused by interactions between the layout and the polishing process, can result in electrical opens, high resistance contacts, electrical shorts, or other leakage paths in the integrated circuits. Traditionally, tiling has been used in forming semiconductor devices to help solve the varying height problem. Tiles are printed dummy features used to fill in the low areas caused by circuitry that is less densely laid out on one portion of a semiconductor device as compared to another portion that has circuitry more densely laid out.
One type of semiconductor device includes an optical device portion and an electronic device portion. This device type may include trenches of two or more depths. One trench, a conventional Shallow Trench Isolation (STI) pattern is patterned using a negative tone mask. A second trench is patterned using a positive tone mask. The tones are opposite to prevent the two trenches from interacting. Also, the negative tone mask may have an extremely low percentage open area which may induce instability in an etched critical dimension (CD) or depth. In addition, the use of tiles may still be important for a subsequent CMP process step, an etch step, or a deposition step.
Therefore, a need exists for a way to solve the above problems.